[coreboot-gerrit] Change in ...coreboot[master]: drivers/intel/fsp1.1: Remove stale comment on bootflow

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32959 )

Change subject: drivers/intel/fsp1.1: Remove stale comment on bootflow
......................................................................

drivers/intel/fsp1.1: Remove stale comment on bootflow

This list is incorrect and not up to date. The FSP1.1 romstage
bootflow is unnecessarily clumsy and instead of trying to update this
comment effort is better spend making the bootflow more streamlined.

Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Frans Hendriks 
---
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
1 file changed, 0 insertions(+), 35 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Frans Hendriks: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index de37950..6ddafd8 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -42,41 +42,6 @@
    const void *data_to_save;
 };

-/*
- * FSP Boot Flow:
- *   1.  src/cpu/x86/16bit/reset.inc
- *   2.  src/cpu/x86/16bit/entry.inc
- *   3.  other modules
- *   4.  src/drivers/intel/fsp1_1/cache_as_ram.inc
- *   5.  src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
- *   6.  FSP binary/TempRamInit
- *   7.  src/drivers/intel/fsp1_1/cache_as_ram.inc - return
- *   8.  src/soc/intel/common/romstage.c/romstage_main
- *   9   src/soc/.../romstage/.../soc_pre_console_init
- *  10   src/console/console.c/console_init
- *  11   src/soc/.../romstage/.../soc_romstage_init
- *  12.  src/mainboard/.../romstage.c/mainboard_romstage_entry
- *  13.  src/soc/intel/common/romstage.c/romstage_common
- *  14   src/soc/.../romstage/.../soc_pre_raminit
- *  15.  FSP binary/MemoryInit
- *  16.  src/soc/intel/common/romstage.c/romstage_common - return
- *  17.  src/mainboard/.../romstage.c/mainboard_romstage_entry - return
- *  18.  src/soc/intel/common/romstage.c/romstage_main - return
- *  19.  src/soc/intel/common/stack.c/setup_stack_and_mtrrs
- *  20.  src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
- *       after call to romstage_main
- *  21.  FSP binary/TempRamExit
- *  22.  src/soc/intel/common/romstage.c/romstage_after_car
- *  23.  FSP binary/SiliconInit
- *  24.  src/soc/intel/common/romstage.c/romstage_after_car - return
- *  25.  src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- *  26.  src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- *  27.  FSP binary/FspNotify
- *  28.  src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- *  29.  src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- *  30.  FSP binary/FspNotify
- */
-
 void mainboard_memory_init_params(struct romstage_params *params,
    MEMORY_INIT_UPD *memory_params);
 void mainboard_romstage_entry(struct romstage_params *params);