[coreboot-gerrit] Change in coreboot[master]: arch/x86: unexpose postcar_frame_common_mtrrs()

[Aaron Durbin (Code Review)]

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41101 )

Change subject: arch/x86: unexpose postcar_frame_common_mtrrs()
......................................................................

arch/x86: unexpose postcar_frame_common_mtrrs()

The only caller is contained within the postcar_loader compilation unit.
Therefore, remove postcar_frame_common_mtrrs() from the global symbol
namespace.

Change-Id: I90d308669d13eb2bebf1eca4d47e3f3b4f178714
Signed-off-by: Aaron Durbin 
---
M src/arch/x86/include/arch/romstage.h
M src/arch/x86/postcar_loader.c
2 files changed, 1 insertion(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41101/1

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 0f9a358..74ec7f4 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -42,11 +42,6 @@
 void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);

/*
- * Add a common MTRR setup most platforms will have as a subset.
- */
-void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
-
-/*
  * fill_postcar_frame() is called after raminit completes and right before
  * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
  * to tag memory ranges as cacheable to speed up execution of postcar and
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 2efa7ac..1852edd 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -111,7 +111,7 @@
    postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
 }

-void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
+static void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
 {
    if (pcf->skip_common_mtrr)
    	return;