[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp

[Hung-Te Lin (Code Review)]

Attention is currently required from: Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, Jianjun Wang.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62934 )

Change subject: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp
......................................................................

Patch Set 1:

(1 comment)

File src/soc/mediatek/mt8195/include/soc/memlayout.ld:

https://review.coreboot.org/c/coreboot/+/62934/comment/5dcb1d73_65332d1c 
PS1, Line 33: 4
I think the system won't do an atomic read/write in that case.

Probably better aligned to 8 bytes or even 16 bytes, for example
 0x00104010