EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
......................................................................
Patch Set 7:
@Subrata, this struct is wokred 😊 Do you have ADL_RVP? Or you can find some people to test it if I change the device tree of RVP?
register "PcieRp[6]" = "{
.enabled = 1,
.clksrc = 3,
.clkreq = 4,
}"
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 7
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Gerrit-Comment-Date: Sat, 05 Dec 2020 11:35:45 +0000
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