Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5029
-gerrit
commit f15a86f58746da8779d7ca88e7dfd91998996dbd Author: Duncan Laurie dlaurie@chromium.org Date: Mon Jan 6 12:35:36 2014 -0800
rambi: Update the DPTF configuration
- Add passive thresholds for thermal participants - Disable the charger participant and remove from _TRT
BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and start ESIF framework
Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09 Signed-off-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: https://chromium-review.googlesource.com/181663 Reviewed-by: Aaron Durbin adurbin@chromium.org Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/rambi/acpi/dptf.asl | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 0d5cd65..8dca454 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,11 +1,16 @@ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 40
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 45
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 35 + +#undef DPTF_ENABLE_CHARGER
Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ @@ -13,15 +18,12 @@ Name (DTRT, Package () {
/* CPU and Charger Effect on Temp Sensor 0 */ Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, - Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 },
/* CPU and Charger Effect on Temp Sensor 1 */ Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, - Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 },
/* CPU and Charger Effect on Temp Sensor 2 */ Package () { _SB.DPTF.TCPU, _SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, - Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 }, })
/* Include Baytrail DPTF */