Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35035 )
Change subject: arch/x86: Implement RESET_VECTOR_IN_RAM ......................................................................
Patch Set 18:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35035/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35035/17//COMMIT_MSG@20 PS17, Line 20: Remove the postcar stage.
Disable? It's not really removed, just not built and added.
probably some remains from an older version of this patch. removed it
https://review.coreboot.org/c/coreboot/+/35035/17/Makefile.inc File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35035/17/Makefile.inc@1175 PS17, Line 1175: ifneq
`ifneq (...,y)` is hard to read, the y sticks out. How about `ifeq` and […]
good point; fixed
https://review.coreboot.org/c/coreboot/+/35035/17/src/arch/x86/early_ram.ld File src/arch/x86/early_ram.ld:
https://review.coreboot.org/c/coreboot/+/35035/17/src/arch/x86/early_ram.ld@... PS17, Line 6: /*
Encouraged comment style wants a line break after the /*
i don't particularly like this, since it just adds another line for no gain, but changed for consistency
https://review.coreboot.org/c/coreboot/+/35035/17/src/arch/x86/memlayout.ld File src/arch/x86/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35035/17/src/arch/x86/memlayout.ld@... PS17, Line 57: #include <arch/x86/id.ld>
How does it get into the coreboot. […]
It doesn't. Traditionally this was added to bootblock, but bootblock on AMD fam17h+ works very differently compared to all other architectures; basically PSP puts it into DRAM after optional decompression and the x86 parts starts executing this from DRAM