Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16320
-gerrit
commit 1fa33e10e1e7ad566924d95085bc7e3242bcf987 Author: Andrey Petrov andrey.petrov@intel.com Date: Thu Aug 25 11:06:08 2016 -0700
soc/intel/apollolake: Disable Periodic Retraining per-SKU
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU.
BUG=chrome-os-partner:55466 TEST=run RMT test, pass
Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- src/mainboard/google/reef/romstage.c | 2 ++ src/soc/intel/apollolake/include/soc/meminit.h | 1 + src/soc/intel/apollolake/meminit.c | 2 ++ 3 files changed, 5 insertions(+)
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..964dee4 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -103,6 +103,7 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { @@ -110,6 +111,7 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index c115c4a..06d2b58 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -102,6 +102,7 @@ struct lpddr4_sku { int ch0_dual_rank; int ch1_dual_rank; const char *part_num; + bool disable_periodic_retraining; };
struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..d0e7683 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -254,6 +254,8 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, sku->ch1_dual_rank, lpcfg->swizzle_config); } + + cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; }
void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)