[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Write EIP to secure S3

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42088 )

Change subject: soc/amd/picasso: Write EIP to secure S3
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42088/5/src/soc/amd/picasso/bootblo... 
File src/soc/amd/picasso/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/42088/5/src/soc/amd/picasso/bootblo... 
PS5, Line 110: 	set_caching();
> This is about S3 resume path. The S3 MSR write snapshots core state including MTRRs and CR0. […]

+1 on what Aaron said re. the architectural state of the core.  The BSP will resume w/whatever x86 state exists when the MSR is written, including caching enabled.  If you're familiar with the ability to save away core state to DRAM during C6, then shove it back in when there's activity, I think that's a good analogy.

BTW Raul, I'd move the write to here too.