[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Override DLL values for Kindred

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35041 )

Change subject: mb/google/hatch: Override DLL values for Kindred
......................................................................

mb/google/hatch: Override DLL values for Kindred

New emmc DLL values for Kindred

BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.

Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10
Signed-off-by: Jamie Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/hatch/variants/kindred/overridetree.cb
1 file changed, 45 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb
index a4ca176..38d7e48 100644
--- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb
@@ -49,6 +49,51 @@
    # Enable eMMC HS400
    register "ScsEmmcHs400Enabled" = "1"

+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-14.3.7.
+	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-14.3.8.
+	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x0F10"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-14.3.9.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2F2D2D"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-14.3.10.
+	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C121936"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-14.3.12.
+	# [17:16] stands for Rx Clock before Output Buffer,
+	#         00: Rx clock after output buffer,
+	#         01: Rx clock before output buffer,
+	#         10: Automatic selection based on working mode.
+	#         11: Reserved
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1182D"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-14.3.11.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1414"
+
    device domain 0 on
    	device pci 15.0 on
    		chip drivers/i2c/generic