[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Modify CSE's PCI BAR address

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44211 )

Change subject: soc/intel/cannonlake: Modify CSE's PCI BAR address
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44211/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44211/1//COMMIT_MSG@14 
PS1, Line 14:
> I am guessing you need this for puff? In that case can you please add BRANCH=puff?

The change will be useful for Puff. But, the change is still applicable for all CML platforms even though CB romstage(except FSP-M) doesn't deal with CSE.