[coreboot-gerrit] Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S

[Xiang Wang (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/27430

to look at the new patch set (#3).

Change subject: riscv: src/arch/riscv/bootblock.S
......................................................................

riscv: src/arch/riscv/bootblock.S

Add an interface to support cache as ram.
Initialize stack pointer for each hart.

Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/bootblock.S
1 file changed, 21 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/3