[coreboot-gerrit] [XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code

[Patrick Rudolph (Code Review)]

Attention is currently required from: Jonathan Zhang, Simon Chou, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 )

Change subject: soc/intel/xeon_sp/spr: add ACPI code
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Patch Set 13:

(1 comment)

File src/soc/intel/xeon_sp/spr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/71967/comment/f7449a13_99c00f93 
PS13, Line 387: 	for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
> I do not have such a system. […]

The issue is that SSDT needs to be in sync with DSDT (src/soc/intel/xeon_sp/spr/acpi/uncore.asl) and DSDT only uses CONFIG_MAX_SOCKET, but not hob->PlatformData.numofIIO.