Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Yang Wu, Yidi Lin, Yu-Ping Wu.
Jiaxin Yu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email )
Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ......................................................................
Patch Set 7:
(4 comments)
File src/mainboard/google/corsola/mainboard.c:
https://review.coreboot.org/c/coreboot/+/79064/comment/0b548061_d5def007 : PS7, Line 43: mt_pll_set_aud_div(48 * KHz); We don't use apll clock, so we can remove this.
File src/soc/mediatek/mt8186/include/soc/pll.h:
https://review.coreboot.org/c/coreboot/+/79064/comment/05e0a98f_2e1d9e93 : PS7, Line 499: APLL2_CK_HZ = APLL2_HZ, remove
https://review.coreboot.org/c/coreboot/+/79064/comment/b8208931_5208defb : PS7, Line 531: void mt_pll_set_aud_div(u32 rate); remove
File src/soc/mediatek/mt8186/pll.c:
https://review.coreboot.org/c/coreboot/+/79064/comment/1fc3b6ec_98ad76fc : PS3, Line 591: void mt_pll_set_aud_div(u32 rate) : { : u32 mclk_div; : u32 apll_clock = APLL2_CK_HZ; : int apll1 = 0; : : if (rate % 11025 == 0) { : /* use APLL1 instead */ : apll1 = 1; : apll_clock = APLL1_CK_HZ; : } : /* I2S1 clock */ : mclk_div = (apll_clock / 256 / rate) - 1; : assert(apll_clock == rate * 256 * (mclk_div + 1)); : : if (apll1) { : /* mclk */ : clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, : 7 << 24); : } else { : /* mclk */ : setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, : 7 << 28); : } : }
Leave this part for Jiaxin to review.
We do not use apll clock, remove this.