Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41058 )
Change subject: [WIP][DONOTMERGE]: Use print GPIO DW's for every community ......................................................................
[WIP][DONOTMERGE]: Use print GPIO DW's for every community
Use Tigerlake gpio.c the printing of GPIO pins for all community.We need to define DEBUG_GPIO in the Kconfig and then call gpio_print_pads from anywhere we want to rpint all the gpio pins. The print's are in the form: gpio_padcfg GPP_B_1 [0x6e, 01] DW0 [0x40000400] DW1 [0x0003c119] DW2 [0x00000100] DW3 [0x00000000]
Signed-off-by: Shaunak Saha shaunak.saha@intel.com Change-Id: I351a8d981d4cf495d0de254f6f2a24060551749d --- M src/soc/intel/tigerlake/gpio.c 1 file changed, 55 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41058/1
diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index cfdd0ac..7713535 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -37,39 +37,79 @@ };
/* - * This layout matches the Linux kernel pinctrl map for TGL-LP at: + * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for TGL at: * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c */ static const struct pad_group tgl_community0_groups[] = { - INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */ - INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */ - INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0, "B"), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32, "T"), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64, "A"), /* GPP_A */ +#else + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 3), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 6), /* GPP_A */ +#endif };
static const struct pad_group tgl_community1_groups[] = { - INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */ - INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */ - INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */ - INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96, "S"), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128, "H"), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160, "D"), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192, "U"), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224, "VGPIO"), /* GPP_VGPIO */ +#else + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224), /* GPP_VGPIO */ +#endif };
/* This community is not visible to the OS */ static const struct pad_group tgl_community2_groups[] = { +#if CONFIG(DEBUG_GPIO) + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB, "GPD"), /* GPD */ +#else INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +#endif };
static const struct pad_group tgl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */ - INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256, "C"), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288, "F"), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, "HVCMOS"), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320, "E"), /* GPP_E */ + INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE, "JTAG"), /* GPP_JTAG */ +#else + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ +#endif };
static const struct pad_group tgl_community5_groups[] = { - INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ - INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352, "R"), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK, "SPI"), /* GPP_SPI */ +#else + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +#endif };
static const struct pad_community tgl_communities[] = {