Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37927 )
Change subject: mb/intel/tglrvp: Update FMAP and EC switches ......................................................................
mb/intel/tglrvp: Update FMAP and EC switches
- Update FMAP to reflect 32MB flash regions - Use LPC/ChromeEC controlled switches
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: I3589cc6eb6e6f6ecc6d40e254b67ed3d15aff7aa --- M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/chromeos.fmd 2 files changed, 9 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37927/1
diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 372f6ce..35ee3dd 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -30,17 +30,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - int get_write_protect_state(void) { /* No write protect */ diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd index f4db8b4..bfbd304 100644 --- a/src/mainboard/intel/tglrvp/chromeos.fmd +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -1,10 +1,10 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x1081000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 + SI_ME@0x81000 0x1000000 } - SI_BIOS@0x400000 0xC00000 { + SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x2bffc0 @@ -20,18 +20,18 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 + SMMSTORE@0x5d0000 0x40000 RW_LEGACY(CBFS)@0x610000 0x1c0000 WP_RO@0x7d0000 0x430000 { - RO_VPD(PRESERVE)@0x0 0x4000 + RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40