Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39201
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: pin mux for Camera ......................................................................
mb/intel/tglrvp: pin mux for Camera
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from OS console
media-ctl -V ""Intel IPU6 CSI-2 5":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI-2 5":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""ov8856 18-0010":0 -> "Intel IPU6 CSI-2 5":0[1]" media-ctl -V ""Intel IPU6 CSI2 BE":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [crop:(0,0)/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""Intel IPU6 CSI-2 5":1 -> "Intel IPU6 CSI2 BE":0[1]" media-ctl -l ""Intel IPU6 CSI2 BE":1 -> "Intel IPU6 CSI2 BE capture":0[1]" yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39201/2