Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50451 )
Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50451/comment/013b1095_fa9aff95 PS2, Line 10: I renamed Misc1 and Misc2 to HPET_L and HPET_H.
I'm struggling to find anything in the PPR to support this. […]
IOx00C01_x0A [Intr_Misc1Map] (FCH::IO::IntrMisc1Map) 7:0 HPET. Read-write. Reset: 00h. Writes to this register update the bits in FCH::TMR::HPET::TMR0_CONF_CAP_H [7:0], FCH::TMR::HPET::TMR1_CONF_CAP_H [7:0] and FCH::TMR::HPET::TMR2_CONF_CAP_H [7:0];
IOx00C01_x0B [Intr_Misc2Map] (FCH::IO::IntrMisc2Map) HPET. Read-write. Reset: 00h. Writes to this register update this bits in FCH::TMR::HPET::TMR0_CONF_CAP_H [15:8], FCH::TMR::HPET::TMR1_CONF_CAP_H [15:8] and FCH::TMR::HPET::TMR2_CONF_CAP_H [15:8];
HPETx00000104 (FCH::TMR::HPET::TMR0_CONF_CAP_H) 31:0 tmrintroutecap. Read-only. Reset: 00C0_0000h. Indicates which INT entry of IoAPIC can be assigned to the timer interrupt. Read only.
I never knew how the HPET was configured to route interrupts until I actually read the Misc descriptions.
Should I rename HPET_X to something else?
File src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h:
https://review.coreboot.org/c/coreboot/+/50451/comment/946e85ce_0aa4545a PS1, Line 61: #define PIRQ_UART2 0x78 /* UART2 */ : #define PIRQ_UART3 0x79 /* UART3 */
By don't exist, do you perhaps mean that they're not pinned out for FP6 and are made unavailable? ( […]
There are only 2 UARTs on the device: UARTx[A:9]000
I can mark these as reserved if you have sent a request to update the PPR.