[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 5:

(1 comment)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/d219d82b_f4a510af 
PS4, Line 572: Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> I'd prefer if you could mention doc#723158 here as well.

Hmm, the CL just facilitates to modify PmcUsb2PhySusPgEnable UPD. In general, the UPD can be modified for any other reason if required. It is better the motivation details be part of CL which actually enables the UPD. Agreed?