EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )
Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37685/5/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/37685/5/src/mainboard/google/dralli... PS5, Line 56: MISCCFG_ENABLE_GPIO_PM_CONFIG
This is not disabling GPIO PM config. Instead it is being enabled.
my fault this should pass 0 not MISCCFG_ENABLE_GPIO_PM_CONFIG
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 160:
Can you please add a comment to indicate what this method does? and what the arg is?
sure.
https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... PS5, Line 165: _SB.PCI0.CGPM
Just "CGPM" should work?
yes :) I just copy paste