[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Intel Xeon Scalable Processor support

[Anjaneya "Reddy" Chagam (Code Review)]

Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )

Change subject: soc/intel: Add Intel Xeon Scalable Processor support
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Patch Set 43:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
PS41, Line 33: 		.CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
             : 		.CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
> I can't agree to that and here is why: […]

No disconnect on your recommendation!! There is regression with this change - hangs post silicon init phase and I prefer to focus on this after initial merge.

This whole thing will be moot once we move away from using FspTempRamInit which needs to be the focus.