[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )

Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
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Patch Set 6:

(1 comment)

https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... 
File src/soc/intel/common/block/gpio/gpio.c:

https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... 
PS6, Line 286: 		}
Can we add an soc callback that returns the pad conf?

uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg)

default weak implementation would be:

uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg)
{
  return reg;
}

Then SoC specific implementation can do its own fixups internally instead of littering the common code.