[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake/acpi: Only offer D3Cold when using S0

[Sean Rhodes (Code Review)]

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59024 )

Change subject: soc/intel/tigerlake/acpi: Only offer D3Cold when using S0
......................................................................

soc/intel/tigerlake/acpi: Only offer D3Cold when using S0

Signed-off-by: Sean Rhodes 
Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4
---
M 3rdparty/blobs
M src/soc/intel/tigerlake/acpi/tcss_dma.asl
2 files changed, 27 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59024/1

diff --git a/3rdparty/blobs b/3rdparty/blobs
index f388b67..f836ff3 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328
+Subproject commit f836ff362b0411ab6c9e580b1e32760aa6ea7e31
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index 273a71e..e7707bb 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -25,26 +25,38 @@

Name (STAT, 0x1)  /* Variable to save power state 1 - D0, 0 - D3C */

+/*
+ * The lowest D-state supported:
+ * 0x03 = D3Hot  (S3)
+ * 0x04 = D3Cold (S0)
+ */
+
 Method (_S0W, 0x0)
 {
-	Return (0x4)
-}
-
-Method (_PR0)
-{
-	If (DUID == 0) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
+	If (UNICORN)
+		Return (0x4)
    } Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
+		Return (0x03)
    }
 }

-Method (_PR3)
-{
-	If (DUID == 0) {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
-	} Else {
-		Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
+If (UNICORN) {
+	Method (_PR0)
+	{
+		If (DUID == 0) {
+			Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
+		}
+	}
+
+	Method (_PR3)
+	{
+		If (DUID == 0) {
+			Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT1 })
+		}
    }
 }