[coreboot-gerrit] [XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config

[Johnny Lin (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, Subrata Banik, TangYiwei, Tim Chu.

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email )

Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
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Patch Set 3:

(1 comment)

Patchset:

PS1:
> > I based on the same upstream tip and pick your latest 2 changes: […]

I pick all 4 cls:
77594/2, 77557/3, 77556/5, 77295/11 but doesn't work. because CB:77556 save_memory_training_data() is only being run after FSP-M and not after FSP-S, for our case there is no FSP_NON_VOLATILE_STORAGE_HOB can be stashed.
at romstage:
[SPEW ]  Calling FspMemoryInit: 0xff058f30
..
[ERROR]  FSP_NON_VOLATILE_STORAGE_HOB missing!
[SPEW ]  FspMemoryInit returned 0x00000000

at ramstage:
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 1367 / 5984 ms
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 3000000 (65536 bytes)
[INFO ]  MRC: No data in cbmem for 'RW_MRC_CACHE'.

Do I need to select MRC_WRITE_NV_LATE or anything?