Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45325 )
Change subject: nb/intel/ironlake: Reserve gap betwen TSEG and BGSM ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... File src/northbridge/intel/ironlake/northbridge.c:
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... PS2, Line 137: it uncacheable, though, for easier MTRR allocation. */ There should be no gap at all, at least that's what the memory map in 322910-003 says. I'd suspect a bug in raminit code, but I don't mind this as a stop-gap solution. However, I'd print a warning/notice about it.