Andy Ebrahiem has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86145?usp=email )
Change subject: mb/supermicro: add support for x13sae-f ......................................................................
mb/supermicro: add support for x13sae-f
Change-Id: If823a27071f282adc122c0bcd910161ae1ba95a3 Signed-off-by: Andy andy@9elements.com --- A src/mainboard/supermicro/x13sae-f/Kconfig A src/mainboard/supermicro/x13sae-f/Kconfig.name A src/mainboard/supermicro/x13sae-f/Makefile.inc A src/mainboard/supermicro/x13sae-f/board_info.txt A src/mainboard/supermicro/x13sae-f/bootblock.c A src/mainboard/supermicro/x13sae-f/devicetree.cb A src/mainboard/supermicro/x13sae-f/dsdt.asl A src/mainboard/supermicro/x13sae-f/mainboard.c A src/mainboard/supermicro/x13sae-f/romstage.c 9 files changed, 115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/86145/1
diff --git a/src/mainboard/supermicro/x13sae-f/Kconfig b/src/mainboard/supermicro/x13sae-f/Kconfig new file mode 100644 index 0000000..4bc7369 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Kconfig @@ -0,0 +1,49 @@ +# ## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SUPERMICRO_X13SAE_F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_RAPTORLAKE_PCH_S + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_UART_8250IO + # select DRIVERS_ASPEED_AST2050 + # select DRIVERS_ASPEED_AST_COMMON + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_IFD_BIN + select HAVE_INTEL_FSP + select HAVE_GBE_BIN + select MAINBOARD_USES_IFD_GBE_REGION + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6791D + select HAVE_EM100_SUPPORT + + +config MAINBOARD_DIR + string + default "supermicro/x13sae-f" + +config MAINBOARD_PART_NUMBER + string + default "X13SAE-F" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + +config GBE_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" + +config SUPERIO_NUVOTON_ENABLE_UART + bool "Enable SuperIO UART for debugging" + default y + + + +# endif \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/Kconfig.name b/src/mainboard/supermicro/x13sae-f/Kconfig.name new file mode 100644 index 0000000..9d60338 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SUPERMICRO_X13SAE_F + bool "X13SAE-F" diff --git a/src/mainboard/supermicro/x13sae-f/Makefile.inc b/src/mainboard/supermicro/x13sae-f/Makefile.inc new file mode 100644 index 0000000..82cb3a1 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/board_info.txt b/src/mainboard/supermicro/x13sae-f/board_info.txt new file mode 100644 index 0000000..0da68e7 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.supermicro.com/de/products/motherboard/x13sae-f +ROM IC: MX25L25673G +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes +Release year: 2022 \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/bootblock.c b/src/mainboard/supermicro/x13sae-f/bootblock.c new file mode 100644 index 0000000..205501c --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <reset.h> + +void bootblock_mainboard_early_init(void) +{ + printk(BIOS_DEBUG, "mainboard_early_init\n"); + board_reset(); +} \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/devicetree.cb b/src/mainboard/supermicro/x13sae-f/devicetree.cb new file mode 100644 index 0000000..a05bb85 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + device domain 0 on + device pci 00.0 on end + device pci 15.0 on end + end +end \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/dsdt.asl b/src/mainboard/supermicro/x13sae-f/dsdt.asl new file mode 100644 index 0000000..584f330 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/supermicro/x13sae-f/mainboard.c b/src/mainboard/supermicro/x13sae-f/mainboard.c new file mode 100644 index 0000000..6344766 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/mainboard.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations mainboard_ops = {}; \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/romstage.c b/src/mainboard/supermicro/x13sae-f/romstage.c new file mode 100644 index 0000000..da4fea6 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/romstage.c @@ -0,0 +1,6 @@ +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + +} \ No newline at end of file