Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42683 )
Change subject: pciexp: retrain PCIe link at lower speed if no link
......................................................................
Patch Set 2:
That setting should be made part of devicetree and thus configurable for each PCIe port.
Are you sure that coreboot isn't just booting too fast and thus the device isn't ready when PCI scanning happens?
--
To view, visit
https://review.coreboot.org/c/coreboot/+/42683
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc
Gerrit-Change-Number: 42683
Gerrit-PatchSet: 2
Gerrit-Owner: Jonathan Kollasch
jakllsch@kollasch.net
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Patrick Rudolph
siro@das-labor.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Tue, 23 Jun 2020 05:51:33 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment