Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32984 )
Change subject: util/superiotool: Add AST2400 ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32984/2/util/superiotool/aspeed.c File util/superiotool/aspeed.c:
https://review.coreboot.org/#/c/32984/2/util/superiotool/aspeed.c@81 PS2, Line 81: }; So 0x1150 is a PCI-to-PCI bridge with 0x2000 "graphics family" device on the secondary?
Is it possible that 0x2000 is disabled or why test 0x1150 at all?
This will currently mislabel almost any AST BMC as "AST2400". You can further read the PCI revision register of 0x2000 device to have this correcly either only detect the AST2400 part or to translate it to a correct silicon name string to display. I don't have datasheets to tell if LPC parts are compatible.
https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/ast/ast_main....
https://review.coreboot.org/#/c/32984/2/util/superiotool/aspeed.c@100 PS2, Line 100: * Together with PCI detection that should be sufficient. From what I remember, outside the config mode, decoders are passive for the configuration registers (all IO at 2e/4e). The entry sequence 0xa5, 0xa5 seems to be unique to AST (in our codebase at least). So, just reading back anything else than 0xff from any global register 0x0..0x2f should alone identify it was AST part that decoded the IO cycle.