Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35313 )
Change subject: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports ......................................................................
Patch Set 2: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/35313/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35313/2//COMMIT_MSG@9 PS2, Line 9: ACS Please spell this out in the beginning (not in the third paragraph).
https://review.coreboot.org/c/coreboot/+/35313/2//COMMIT_MSG@9 PS2, Line 9: Currently it is impossible to enable ACS with AGESA by setting the correct : bit for AmdInitMid phase. AGESA code path does not call the right function : that enables these functionalities. Can a comment be added to the code in question?
https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... PS2, Line 781: 0xB0 E or B?
https://review.coreboot.org/c/coreboot/+/35313/2/src/northbridge/amd/pi/0073... PS2, Line 793: /* Enable ACS capabilities straps including sub-items. From lspci it : * looks like these bits enable: Source Validation and Translation : * Blocking : */ Please use one of the listed styles from the coding style.