[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Fix register lock

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85439?usp=email )

Change subject: soc/intel/xeon_sp/cpx: Fix register lock
......................................................................

soc/intel/xeon_sp/cpx: Fix register lock

Do not use a define for a PCI register to lock a MSR.

The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.

Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/cpx/cpu.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85439/1

diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index d90b8b5..4af20f1 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -118,7 +118,7 @@
    /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
       Lock Turbo. Did FSP-S set this up??? */
    msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
-	msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
+	msr.lo |= BIT31;	/* Lock it */
    wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
 }