Attention is currently required from: Angel Pons.
Hello Arthur Heymans, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58284?usp=email
to look at the new patch set (#4).
Change subject: soc/intel/broadwell: Clarify PCIe Non Common Clock mode ......................................................................
soc/intel/broadwell: Clarify PCIe Non Common Clock mode
The "force ASPM" setting actually controls Non Common Clock mode with Spread Spectrum Clocking. Rename the associated variables accordingly and expand the comments according to document 535127 (BDW PCH-LP BS).
Change-Id: I4174f6302d62aea81aa74515e2e3135ee324aa7c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pch/pcie.c 6 files changed, 23 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/58284/4