[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#3) to the change originally created by jitao shi. ( https://review.coreboot.org/c/coreboot/+/38400 )

Change subject: soc/mediatek/mt8183: reduce the hbp and hfp for phy timing
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soc/mediatek/mt8183: reduce the hbp and hfp for phy timing

There are some extra data tranfers in dsi.
ex. LPX, hs_prepare, hs_zero, hs_exit and the sof/eof of dsi packet.
This signal will enlarge the line time. So the real frame on dsi bus
will be lower than calculated by video timing.

So dsi driver reduces the hbp and hfp to keep the line time:

hbp = hbp - phy_extra * hbp / (hbp + hfp)
 hfp = hfp - phy_extra * hfp / (hbp + hfp)

Also refactored to sync with DSI driver in kernel upstream.

BUG=b:144824303
BRANCH=kukui
TEST=Boots and sees firmware screen on krane and jacuzzi

Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227
Signed-off-by: Jitao Shi 
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M src/soc/mediatek/common/dsi.c
1 file changed, 41 insertions(+), 43 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38400/3