Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Martin Roth, Matt DeVillier, Tim Van Patten.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Martin Roth, Matt DeVillier, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78231?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+1 by Tim Van Patten, Code-Review+2 by Felix Held, Code-Review+2 by Jon Murphy, Verified+1 by build bot (Jenkins)
Change subject: soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption ......................................................................
soc/amd/common/vboot: Fix PSP verstage timestamps after TSC adoption
Commit 26d54b7 (soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for SOC_AMD_COMMON_BLOCK_TSC) updated all the AMD SoCs with Zen-based CPU cores to use TSC_MONOTONIC_TIMER. The same change adjusted the PSP Verstage timestamps (in microseconds) to the x86 TSC rate. But it included only the base_time during the adjustment leaving the individual entry timestamp. This leads to incorrectly adjusted PSP Verstage timestamps. Fix the adjustment logic.
BUG=None TEST=Build and boot to OS in Skyrim. Ensure that the PSP Verstage timestamps in cbmem -t output are adjusted correctly. Before this change: 5:start of verified boot 67,890 (69,936) 503:starting to initialize TPM 67,890 (0) 504:finished TPM initialization 67,902 (12) 505:starting to verify keyblock/preamble (RSA) 67,906 (3) 506:finished verifying keyblock/preamble (RSA) 67,984 (77) 511:starting TPM PCR extend 67,984 (0) 512:finished TPM PCR extend 67,992 (7) 513:starting locking TPM 67,992 (0) 514:finished locking TPM 67,995 (3) 6:end of verified boot 67,995 (0) 11:start of bootblock 572,152 (504,156)
After this change: 5:start of verified boot 71,000 (73,040) 503:starting to initialize TPM 71,065 (65) 504:finished TPM initialization 101,506 (30,441) 505:starting to verify keyblock/preamble (RSA) 110,624 (9,118) 506:finished verifying keyblock/preamble (RSA) 297,101 (186,477) 511:starting TPM PCR extend 297,297 (196) 512:finished TPM PCR extend 315,338 (18,041) 513:starting locking TPM 315,341 (3) 514:finished locking TPM 322,922 (7,581) 6:end of verified boot 322,943 (21) 11:start of bootblock 570,296 (247,353)
Change-Id: I3e52bef22f65596152f29c511bed680427660ff5 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/amd/common/vboot/vboot_bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/78231/2