[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/ptl: Enable UFS functionality by adding IRQ programming

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85536?usp=email )

Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
......................................................................

soc/intel/ptl: Enable UFS functionality by adding IRQ programming

This commit adds the necessary IRQ programming for the UFS controller,
addressing an issue where the device was not operational after booting
to the OS.

BUG=b:382243957
TEST=Built and booted google/fatcat successfully, verifying UFS
functionality.

Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/fsp_params.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85536/1

diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c
index e0b0adf..dfc47c6 100644
--- a/src/soc/intel/pantherlake/fsp_params.c
+++ b/src/soc/intel/pantherlake/fsp_params.c
@@ -199,6 +199,14 @@
    		ANY_PIRQ(PCI_DEVFN_CSE_4),
    	},
    },
+#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
+	{
+		.slot = PCI_DEV_SLOT_UFS,
+		.fns = {
+			ANY_PIRQ(PCI_DEVFN_UFS),
+		},
+	},
+#endif
    {
    	.slot = PCI_DEV_SLOT_SIO1,
    	.fns = {