[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Disable XHCI LFPS power management

[Marx Wang (Code Review)]

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40255 )

Change subject: soc/intel/apollolake: Disable XHCI LFPS power management
......................................................................

soc/intel/apollolake: Disable XHCI LFPS power management

Provide the option to disable XHCI LFPS power managemnt.
If the option is set in device tress, the bit[7:4] in XHCI
MMIO BAR + offset 0x80A4(PMCTRL_REG) will be updated from
default 9 to 0

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bit[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Marx Wang 
Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
2 files changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/40255/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 2c8737f..5633493 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -99,6 +99,10 @@
 /* IOSF Gasket Backbone Local Clock Gating Enable */
 #define IOSFGBLCGE		(1 << 0)

+#define CFG_XHCPMCTRL           0x80a4
+/* BIT[7:4] LFPS periodic sampling for USB3 Ports */
+#define LFPS_PM_DISABLE_MASK    0xFFFFFF0F
+
 const char *soc_acpi_name(const struct device *dev)
 {
    if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -830,6 +834,37 @@
    return !!dev->enabled;
 }

+static void config_xhci_lfps_pm(void)
+{
+	static struct soc_intel_apollolake_config *cfg;
+	struct device *dev = SA_DEV_ROOT;
+
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+		return;
+	}
+
+	cfg = dev->chip_info;
+
+	if (cfg->DisableXhciLfpsPM)
+	{
+		uint32_t *addr;
+		const struct resource *res;
+		uint32_t reg;
+		struct device *xhci_dev = PCH_DEV_XHCI;
+
+		res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
+		addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL);
+		reg = read32(addr);
+		printk(BIOS_INFO, "XHCI PM control reg=0x%x.\n", reg);
+		if (reg){
+			reg &= LFPS_PM_DISABLE_MASK;
+			write32(cfg, reg);
+			printk(BIOS_INFO, "XHCI PM control reg updated to=0x%x.\n", reg);
+		}
+	}
+}
+
 void platform_fsp_notify_status(enum fsp_notify_phase phase)
 {
    if (phase == END_OF_FIRMWARE) {
@@ -877,6 +912,11 @@
    			IOSFGBLCGE;
    		write32(cfg, reg);
    	}
+
+		/*
+		 * Disable XHCI LFPS power management if the option in dev tree is set
+		 */
+		config_xhci_lfps_pm();
    }
 }

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index c7974a6..00d5764 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -184,6 +184,14 @@
     * the Upd parameter VtdEnable.
     */
    uint8_t enable_vtd;
+
+	/* Options to disable control the OFF time for the LFPS periodic sampling
+	 * for USB3 Ports. Default is 9: OFF time is 9ms
+	 *
+	 * Set 1 to update XHCI host MMIO BAR + PMCTRL_REG(0x80A4 bits[7:4)] to 0
+	 * 0:FALSE(Default), 1:True.
+	*/
+	uint8_t DisableXhciLfpsPM;
 };

typedef struct soc_intel_apollolake_config config_t;