Attention is currently required from: Harsha B R, Usha P, Eric Lai.
Hello build bot (Jenkins), Sridhar Siricilla, Usha P, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72647
to look at the new patch set (#3).
Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices ......................................................................
mb/intel/mtlrvp: Add chip configuration for I2C devices
This patch adds below chip configuration for I2C devices for mtlrvp.
+-----------+--------------------+-------------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | +-----------+--------------------+-------------+ | I2C0 | 0:0x15:0 | CAM1 | +-----------+--------------------+-------------+ | I2C1 | 0:0x15:1 | CAM0 | +-----------+--------------------+-------------+ | I2C2 | 0:0x15:2 | NC | +-----------+--------------------+-------------+ | I2C3 | 0:0x15:3 | HID | +-----------+--------------------+-------------+ | I2C4 | 0:0x15:4 | NC | +-----------+--------------------+-------------+ | I2C5 | 0:0x15:5 | NC | +-----------+--------------------+-------------+
BUG=b:224325352 BRANCH=None TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS
Signed-off-by: Harsha B R harsha.b.r@intel.com Change-Id: Ia5964472be902041f961187c0072a89055badd4f Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/72647/3