Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47576 )
Change subject: nb/intel/sandybridge: Rename `read_training` function ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/47576/2/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47576/2/src/northbridge/intel/sandy... PS2, Line 1315: Compensate the skew between DQS and DQs. : * : * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. : * The controller has to measure and compensate this skew for every byte-lane. By delaying : * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed : * that one byte-lane's DQs signals have the same routing delay. : * : * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling : * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates : * over all possible values to do a full phase shift and issues read commands. With DQS and : * DQ in phase the data being read is expected to alternate on every byte: : * : * 0xFF 0x00 0xFF ... : * : * Once the controller has detected this pattern a bit in the result register is set for the : * current phase shift. Is this still accurate?