Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10991
-gerrit
commit a35ab5be0183596a4a17a6a54769f3a8f01df569 Author: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com Date: Thu Jul 9 00:32:32 2015 -0700
braswell: clean up _PR entries
All _PR entries needs to be changed from CPU# to CP## so that it can support more cores.
BRANCH=none BUG=chrome-os-partner:38734 TEST=build and boot cyan/strago boards.
Change-Id: I80a79ec8edbce46826140470645b7532ae361f91 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1 Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c Original-Signed-off-by: Jagadish Krishnamoorthy jagadish.krishnamoorthy@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/285700 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/braswell/acpi/cpu.asl | 38 ++++++++++++++++---------------- src/soc/intel/braswell/acpi/dptf/cpu.asl | 38 ++++++++++++++++---------------- 2 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index d487974..0ae51f2 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -30,22 +30,22 @@ #define DPTF_CPU_ACTIVE_AC4 50
/* These devices are created at runtime */ -External (_PR.CPU0, DeviceObj) -External (_PR.CPU1, DeviceObj) -External (_PR.CPU2, DeviceObj) -External (_PR.CPU3, DeviceObj) +External (_PR.CP00, DeviceObj) +External (_PR.CP01, DeviceObj) +External (_PR.CP02, DeviceObj) +External (_PR.CP03, DeviceObj)
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (_PR.CPU0, 0x81) /* _CST */ - Notify (_PR.CPU1, 0x81) /* _CST */ + Notify (_PR.CP00, 0x81) /* _CST */ + Notify (_PR.CP01, 0x81) /* _CST */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (_PR.CPU2, 0x81) /* _CST */ - Notify (_PR.CPU3, 0x81) /* _CST */ + Notify (_PR.CP02, 0x81) /* _CST */ + Notify (_PR.CP03, 0x81) /* _CST */ } }
@@ -53,12 +53,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (_PR.CPU0, 0x80) /* _PPC */ - Notify (_PR.CPU1, 0x80) /* _PPC */ + Notify (_PR.CP00, 0x80) /* _PPC */ + Notify (_PR.CP01, 0x80) /* _PPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (_PR.CPU2, 0x80) /* _PPC */ - Notify (_PR.CPU3, 0x80) /* _PPC */ + Notify (_PR.CP02, 0x80) /* _PPC */ + Notify (_PR.CP03, 0x80) /* _PPC */ } }
@@ -66,12 +66,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (_PR.CPU0, 0x82) /* _TPC */ - Notify (_PR.CPU1, 0x82) /* _TPC */ + Notify (_PR.CP00, 0x82) /* _TPC */ + Notify (_PR.CP01, 0x82) /* _TPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (_PR.CPU2, 0x82) /* _TPC */ - Notify (_PR.CPU3, 0x82) /* _TPC */ + Notify (_PR.CP02, 0x82) /* _TPC */ + Notify (_PR.CP03, 0x82) /* _TPC */ } }
@@ -79,10 +79,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {_PR.CPU0, _PR.CPU1, _PR.CPU2, _PR.CPU3}) + Return (Package() {_PR.CP00, _PR.CP01, _PR.CP02, _PR.CP03}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {_PR.CPU0, _PR.CPU1}) + Return (Package() {_PR.CP00, _PR.CP01}) } Else { - Return (Package() {_PR.CPU0}) + Return (Package() {_PR.CP00}) } } diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 9b1930b..018144c 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (_PR.CPU0._TSS, MethodObj) -External (_PR.CPU0._TPC, MethodObj) -External (_PR.CPU0._PTC, PkgObj) -External (_PR.CPU0._TSD, PkgObj) -External (_PR.CPU0._PSS, MethodObj) +External (_PR.CP00._TSS, MethodObj) +External (_PR.CP00._TPC, MethodObj) +External (_PR.CP00._PTC, PkgObj) +External (_PR.CP00._TSD, PkgObj) +External (_PR.CP00._PSS, MethodObj) External (_SB.DPTF.CTOK, MethodObj)
Device (B0DB) @@ -24,8 +24,8 @@ Device (B0DB)
Method (_TSS) { - If (CondRefOf (_PR.CPU0._TSS)) { - Return (_PR.CPU0._TSS) + If (CondRefOf (_PR.CP00._TSS)) { + Return (_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (B0DB)
Method (_TPC) { - If (CondRefOf (_PR.CPU0._TPC)) { - Return (_PR.CPU0._TPC) + If (CondRefOf (_PR.CP00._TPC)) { + Return (_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (B0DB)
Method (_PTC) { - If (CondRefOf (_PR.CPU0._PTC)) { - Return (_PR.CPU0._PTC) + If (CondRefOf (_PR.CP00._PTC)) { + Return (_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (B0DB)
Method (_TSD) { - If (CondRefOf (_PR.CPU0._TSD)) { - Return (_PR.CPU0._TSD) + If (CondRefOf (_PR.CP00._TSD)) { + Return (_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (B0DB)
Method (_TDL) { - If (CondRefOf (_PR.CPU0._TSS)) { - Store (SizeOf (_PR.CPU0._TSS ()), Local0) + If (CondRefOf (_PR.CP00._TSS)) { + Store (SizeOf (_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (B0DB)
Method (_PSS) { - If (CondRefOf (_PR.CPU0._PSS)) { - Return (_PR.CPU0._PSS) + If (CondRefOf (_PR.CP00._PSS)) { + Return (_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (_SB.MPDL)) { Return (_SB.MPDL) - } ElseIf (CondRefOf (_PR.CPU0._PSS)) { - Store (SizeOf (_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (_PR.CP00._PSS)) { + Store (SizeOf (_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else {