Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45654 )
Change subject: soc/intel: Make GPIO ASL helper function unified across SoC ......................................................................
soc/intel: Make GPIO ASL helper function unified across SoC
List of changes: 1. Make CNL gpio_op.asl unified as TGL gpio_op.asl 2. Refer GPIO state macros from intelblocks/gpio_defs.h 3. Delete unused gpio_common.h from CNL SoC 4. Make ASL helper function like GRXS, GTXS, STXS, CTXS unified across ICL, JSL, SKL
TEST=Able to build and boot CNL and CML platform. 1) Dump and disassemble DSDT, verify unified methods like GRXS, GTXS etc. are there. 2) Verify no ACPI error seen while running 'dmesg` from console.
Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/gpio_op.asl D src/soc/intel/cannonlake/include/soc/gpio_common.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/jasperlake/acpi/gpio_op.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_op.asl 9 files changed, 27 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45654/1
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 3c0ed66..8af1e0c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h>
/* * Get GPIO Value @@ -11,7 +12,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } @@ -27,7 +28,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, VAL0, Local0) + Local0 = PAD_CFG0_TX_STATE & VAL0
Return (Local0) } @@ -43,7 +44,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 = PAD_CFG0_TX_STATE | VAL0 }
/* @@ -57,7 +58,7 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 = ~PAD_CFG0_TX_STATE & VAL0 }
/* @@ -76,10 +77,9 @@ { VAL0, 32 } - Store (VAL0, Local0) - And (Not (GPIOPADMODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) + Local0 = ~PAD_CFG0_MODE_MASK & VAL0 + Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + VAL0 = Local0 | Arg1 }
/* @@ -97,10 +97,10 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_TX_DISABLE | VAL0 } }
@@ -119,9 +119,9 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIORXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_RX_DISABLE | VAL0 } } diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h deleted file mode 100644 index c11ef50..0000000 --- a/src/soc/intel/cannonlake/include/soc/gpio_common.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ -#define _SOC_CANNONLAKE_GPIO_COMMON_H_ - -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIORXBUFDIS_MASK 0x200 - -#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 9b1690e..e7769b5 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h>
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index a1f51d1..bd68b04 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h>
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 43aa83c..823f9cc 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h> #include <soc/gpio_defs.h> #include <soc/irq.h> #include <soc/pcr_ids.h> @@ -114,7 +115,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 57701e1..577ca5f 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -257,6 +257,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600
-#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 #endif diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl index 683686f..8af1e0c 100644 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h>
/* * Get GPIO Value @@ -76,9 +77,8 @@ { VAL0, 32 } - Local0 = VAL0 - Local0 = ~PAD_CFG0_MODE_MASK & Local0 - Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + Local0 = ~PAD_CFG0_MODE_MASK & VAL0 + Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK VAL0 = Local0 | Arg1 }
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 60e1cf5..5dba1bb 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h> #include <soc/gpio.h>
-#define GPIOTXSTATE_MASK 0x1 -#define GPIORXSTATE_MASK 0x1 - Device (GPIO) { Name (_HID, "INT344B") @@ -119,7 +117,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } @@ -135,7 +133,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + Local0 = PAD_CFG0_TX_STATE & VAL0
Return (Local0) } @@ -151,7 +149,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 = PAD_CFG0_TX_STATE | VAL0 }
/* @@ -165,5 +163,5 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 = ~PAD_CFG0_TX_STATE & VAL0 } diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl index f7332aa..8af1e0c 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_op.asl +++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h>
/* * Get GPIO Value