Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 63:
(3 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/bcdc27b6_65b5c5c1
PS62, Line 44:
one space is enough (applies to all ports)
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/2984d2c8_9d56e39d
PS62, Line 47: }"
tab (applies to all ports)
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/bfc054ae_a3aa46ea
PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{
: .flags = PCIE_RP_CLK_SRC_UNUSED,
: }"
: register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
Since we now know that a free-running CLKSRC doesn't use any CLKREQ, how about expressing this as […]
Echo to Furquan.
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