Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro...
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro...
PS28, Line 157: CONFIG_MAX_ROOT_PORTS
What do you mean? I think Kconfig if fine.
just use CONFIG_MAX_ROOT_PORTS above in pcie_rp_init:
Instead of this:
static void pcie_rp_init(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type,
const struct pcie_rp_config *cfg, size_t cfg_count)
{
unsigned int i;
for (i = 0; i < cfg_count; i++) {
do this:
static void pcie_rp_init(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type,
const struct pcie_rp_config *cfg)
{
unsigned int i;
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
--
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