[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: add processor power limits control support

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )

Change subject: soc/intel/jasperlake: add processor power limits control support
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... 
File src/soc/intel/jasperlake/systemagent.c:

https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy... 
PS1, Line 69: mdelay(1);
Can you please add a comment regarding why the delay is required? Does BIOS reset CPL turn on some resources required before setting power limits? Is this requirement captured in a doc?