HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33504
Change subject: MSR: Move MSR_PLATFORM_INFO to common place ......................................................................
MSR: Move MSR_PLATFORM_INFO to common place
Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 13 files changed, 2 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 6c5cc31..4ee294f 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -30,8 +30,6 @@
#define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4ebbe18..b7ce762 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -43,8 +43,6 @@ #define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5..cc830a9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -30,8 +30,6 @@ #define FERR_ENABLE (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434..795ab79 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -30,8 +30,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce..a4657c5 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,9 +25,10 @@ #define CPUID_DCA (1 << 18) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b75..dd333e8 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif
-#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c..8b35355 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820..a121180 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -18,7 +18,6 @@ #define _SOC_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa2..58dcba8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,7 +18,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..655b325 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,7 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H
#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 0d469c4..d63257b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -20,7 +20,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index b8fe7fe..8ace3f6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index e4b8c50..6ae0bae 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -19,7 +19,6 @@ #define _SOC_MSR_H_
#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610