Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7199
-gerrit
commit 97716b60d86f8715cd0e065b2d38269d9cc04dc3 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sat Oct 25 15:18:25 2014 +0200
i82801gx: Handle whole FADT in southbridge.
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks.
Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/arch/x86/boot/acpi.c | 5 ++-- src/arch/x86/include/arch/acpi.h | 3 +- src/mainboard/apple/macbook21/devicetree.cb | 3 ++ src/mainboard/apple/macbook21/fadt.c | 27 ----------------- src/mainboard/getac/p470/devicetree.cb | 4 +++ src/mainboard/getac/p470/fadt.c | 28 ----------------- src/mainboard/ibase/mb899/devicetree.cb | 3 ++ src/mainboard/ibase/mb899/fadt.c | 32 -------------------- src/mainboard/intel/d945gclf/devicetree.cb | 2 ++ src/mainboard/intel/d945gclf/fadt.c | 28 ----------------- src/mainboard/kontron/986lcd-m/devicetree.cb | 2 ++ src/mainboard/kontron/986lcd-m/fadt.c | 33 -------------------- src/mainboard/lenovo/t60/devicetree.cb | 3 ++ src/mainboard/lenovo/t60/fadt.c | 28 ----------------- src/mainboard/lenovo/x60/devicetree.cb | 4 +++ src/mainboard/lenovo/x60/fadt.c | 28 ----------------- src/mainboard/roda/rk886ex/devicetree.cb | 4 +++ src/mainboard/roda/rk886ex/fadt.c | 28 ----------------- src/southbridge/intel/i82801gx/chip.h | 3 ++ src/southbridge/intel/i82801gx/lpc.c | 45 +++++++++++++++++----------- 20 files changed, 59 insertions(+), 254 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..baea65c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -660,7 +660,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 3; + header->revision = 4; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -680,8 +680,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) fadt->preferred_pm_profile = PM_DESKTOP; }
- southbridge_fill_fadt(fadt); - mainboard_fill_fadt(fadt); + acpi_fill_fadt(fadt);
header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index ff59a01..313bdf1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -495,8 +495,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); #if IS_ENABLED(CONFIG_COMMON_FADT) -void southbridge_fill_fadt(acpi_fadt_t * fadt); -void mainboard_fill_fadt(acpi_fadt_t * fadt); +void acpi_fill_fadt(acpi_fadt_t * fadt); #endif
void update_ssdt(void *ssdt); diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 5b11b52..9509c81 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -69,6 +69,9 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "1"
register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller subsystemid 0x8384 0x7680 diff --git a/src/mainboard/apple/macbook21/fadt.c b/src/mainboard/apple/macbook21/fadt.c deleted file mode 100644 index 314153d..0000000 --- a/src/mainboard/apple/macbook21/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; -} diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index fd97445..d88304e 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -60,6 +60,10 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0"
+ register "c3_latency" = "85" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on # High Definition Audio ioapic_irq 2 INTA 0x16 end diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c deleted file mode 100644 index 8722743..0000000 --- a/src/mainboard/getac/p470/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index af04398..ccf6405 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -32,6 +32,9 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x1"
+ register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 end # High Definition Audio diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c deleted file mode 100644 index f2770a5..0000000 --- a/src/mainboard/ibase/mb899/fadt.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index acbde2a..9f9afff 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -52,6 +52,8 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on ioapic_irq 2 INTA 0x16 end # High Definition Audio diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c deleted file mode 100644 index 74a0e7e..0000000 --- a/src/mainboard/intel/d945gclf/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 069660c..b701f78 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -32,6 +32,8 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on ioapic_irq 2 INTA 0x16 diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c deleted file mode 100644 index 92bf647..0000000 --- a/src/mainboard/kontron/986lcd-m/fadt.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED - | ACPI_FADT_RESET_REGISTER |ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5e2a4fe..1d5f549 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -69,6 +69,9 @@ chip northbridge/intel/i945 register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/lenovo/t60/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index a067f92..af3d10d 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -67,6 +67,10 @@ chip northbridge/intel/i945 register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/lenovo/x60/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 6e34b6f..8e4a665 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -53,6 +53,10 @@ chip northbridge/intel/i945 register "gpi7_routing" = "2" register "gpe0_en" = "0x20800007"
+ register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/roda/rk886ex/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index c61ec98..589c082 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -59,6 +59,9 @@ struct southbridge_intel_i82801gx_config { uint32_t sata_ports_implemented;
int c4onc3_enable:1; + int docking_supported:1; + int p_cnt_throttling_supported:1; + int c3_latency; };
#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 085906f..21d61e3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -138,7 +138,7 @@ static void i82801gx_pirq_init(device_t dev) static void i82801gx_gpi_routing(device_t dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *chip = dev->chip_info; u32 reg32 = 0;
/* An array would be much nicer here, or some @@ -486,9 +486,11 @@ unsigned long acpi_fill_madt(unsigned long current) return current; }
-void southbridge_fill_fadt(acpi_fadt_t * fadt) +void acpi_fill_fadt(acpi_fadt_t * fadt) { - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *config = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -510,7 +512,7 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0;
@@ -519,56 +521,56 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 0; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 0; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 0; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; @@ -585,14 +587,23 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt)
fadt->cst_cnt = APM_CNT_CST_CONTROL; fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; + fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->iapc_boot_arch = 0x03; + fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED + | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE + | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER + | ACPI_FADT_C2_MP_SUPPORTED); + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } }
static void i82801gx_lpc_read_resources(device_t dev)