Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 65:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/ae177008_17bc71fa
PS65, Line 149: pcie_clk_config_flag
PCIE_RP_CLK_SRC_UNUSED is set as part of root port config and not clock config.
https://review.coreboot.org/c/coreboot/+/48340/comment/f3f3715d_b1073b45
PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
How can FSP/coreboot disable SRC CLK from an external clock chip?
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