Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47188 )
Change subject: mb/purism/librem_mini: Reorganize devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47188/1/src/mainboard/purism/librem... PS1, Line 22: # All SRCCLKREQ pins mapped directly : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : : # Set all SRCCLKREQ pins as free-use : register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80"
are they in use at all? connected to anything?
We had some problems with PCIe clocks not working as intended, which is why these settings are not optimal (but they work, which is what matters). Currently, all clock sources are configured as free-running (not tied to any particular PCIe root port). Most boards don't cross CLKREQ# and CLKSRC, which is why they're directly-mapped.
I figured out how the ClkSrcUsage settings work, and I'll revise these settings later.