[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure Hyperthreading

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39683 )

Change subject: soc/intel/tigerlake: Configure Hyperthreading
......................................................................

soc/intel/tigerlake: Configure Hyperthreading

Configure Hyperthreading based on devicetree

BUG=none
TEST= Build and boot with FSP log and check Hyperthread setting

Signed-off-by: Wonkyu Kim 
Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 5 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f82f13d..1d4bd5f 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -292,6 +292,8 @@
     */
    uint8_t cpu_ratio_override;

+	/* HyperThreadingDisable : Yes (1) / No (0) */
+	uint8_t HyperThreadingDisable;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 95f637e..32f1b03 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -143,8 +143,9 @@
    else
    	m_cfg->TcssItbtPcie3En = 0;

-	/* Enable Hyper Threading */
-	m_cfg->HyperThreading = 1;
+	/* Hyper Threading */
+	m_cfg->HyperThreading = !config->HyperThreadingDisable;
+
    /* Disable Lock PCU Thermal Management registers */
    m_cfg->LockPTMregs = 0;
    /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */