Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74881 )
Change subject: [TEST] [Do Not Merge] Send EOP from payload ......................................................................
[TEST] [Do Not Merge] Send EOP from payload
Signed-off-by: Kapil Porwal kapilporwal@google.com Change-Id: I542f06ad6bb0c34a1757da97dd8a63b052f39c0b --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/mainboard/google/rex/Kconfig M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c 10 files changed, 76 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74881/1
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 5f6a223..53637fe 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -80,6 +80,7 @@ CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, CB_TAG_SMMSTOREV2 = 0x0039, + CB_TAG_CSE_EOP = 0x003b, CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_ACPI_CNVS = 0x0041, CB_TAG_TYPE_C_INFO = 0x0042, @@ -419,6 +420,12 @@ u32 type; };
+struct cb_cse_eop { + uint32_t tag; + uint32_t size; + void (*send)(void); +}; + /* * Handoff the ACPI RSDP */ diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 12d8a13..1bb64fe 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -159,6 +159,7 @@ uint32_t cbfs_ro_mcache_size; uintptr_t cbfs_rw_mcache_offset; uint32_t cbfs_rw_mcache_size; + struct cb_cse_eop *cse_eop; };
extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bcc9530..4edd1bf 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -277,6 +277,11 @@ info->acpi_rsdp = cb_acpi_rsdp->rsdp_pointer; }
+static void cb_parse_cse_eop(void *ptr, struct sysinfo_t *info) +{ + info->cse_eop = (struct cb_cse_eop *)ptr; +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -423,6 +428,9 @@ case CB_TAG_PCIE: cb_parse_pcie(ptr, info); break; + case CB_TAG_CSE_EOP: + cb_parse_cse_eop(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index e646b8b..a665209 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -82,6 +82,7 @@ LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, LB_TAG_SMMSTOREV2 = 0x0039, LB_TAG_TPM_PPI_HANDOFF = 0x003a, + LB_TAG_CSE_EOP = 0x003b, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, @@ -572,4 +573,10 @@ lb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ };
+struct lb_cse_eop { + uint32_t tag; + uint32_t size; + void (*send)(void); +}; + #endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e209e4b..5d33cd7 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -47,4 +47,6 @@ /* Add VBOOT VBNV offsets. */ void lb_table_add_vbnv_cmos(struct lb_header *header);
+void lb_cse_send_eop_and_finalize(void); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index bee389d..1993fbe 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -464,6 +464,18 @@ return (uintptr_t)lb_table_fini(head) - entry; }
+static void fill_cse_eop_info(struct lb_header *head) +{ + struct lb_cse_eop *lb_eop; + + lb_eop = (struct lb_cse_eop *)lb_new_record(head); + + lb_eop->tag = LB_TAG_CSE_EOP; + lb_eop->size = sizeof(*lb_eop); + + lb_eop->send = lb_cse_send_eop_and_finalize; +} + static uintptr_t write_coreboot_table(uintptr_t rom_table_end) { struct lb_header *head; @@ -560,6 +572,8 @@ if (CONFIG(HAVE_ACPI_TABLES)) lb_add_acpi_rsdp(head);
+ fill_cse_eop_info(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 528a2dc..073b5b4 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -27,7 +27,7 @@ select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 - select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
config BOARD_GOOGLE_BASEBOARD_REX def_bool n diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1eb3eff..98908a1 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -107,6 +107,16 @@ request is posted (at CSE .final device operation) and the time coreboot check for its completion (BS_PAYLOAD_LOAD).
+config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on !SOC_INTEL_CSE_SEND_EOP_LATE + depends on !SOC_INTEL_CSE_SEND_EOP_EARLY + depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC + help + Use this config to send End Of Post (EOP) using payload. coreboot supplies a function + pointer, to send EOP, to payload via a coreboot table. + config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 1aa3454..8deef01 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1408,6 +1408,7 @@ void cse_late_finalize(void) { if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) && + !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) && !CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return;
@@ -1434,6 +1435,7 @@ * will be run once the EOP command has successfully been completed. */ if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return;
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index dd67e59..264f3c4 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> +#include <boot/coreboot_tables.h> #include <bootstate.h> #include <console/console.h> #include <intelblocks/cse.h> @@ -301,10 +302,22 @@ do_send_end_of_post(true);
if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) cse_late_finalize(); }
+void lb_cse_send_eop_and_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD)) + return; + + printk(BIOS_INFO, "Sending End-of-POST from the payload!\n"); + + send_cse_eop_with_late_finalize(NULL); +} + +#if !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) /* * Ideally, to give coreboot maximum flexibility, sending EOP would be done as * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must @@ -319,3 +332,4 @@ #else BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, send_cse_eop_with_late_finalize, NULL); #endif +#endif