Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13507
-gerrit
commit b265ac7e40e5e3cec10599ae5a916f5cf3940781 Author: Lee Leahy leroy.p.leahy@intel.com Date: Tue Jan 26 10:06:42 2016 -0800
mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board.
TEST=Build for Galileo CQ-DEPEND=CL:13436 CL:13439
Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/mainboard/intel/galileo/Kconfig | 36 +++++++++++ src/mainboard/intel/galileo/Kconfig.name | 17 +++++ src/mainboard/intel/galileo/Makefile.inc | 16 +++++ src/mainboard/intel/galileo/devicetree.cb | 24 +++++++ src/mainboard/intel/galileo/galileo.html | 100 ++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/romstage.c | 24 +++++++ 6 files changed, 217 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig new file mode 100755 index 0000000..cae136f --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_GALILEO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select PLATFORM_USES_FSP1_1 + select SOC_INTEL_QUARK + +config MAINBOARD_DIR + string + default intel/galileo + +config MAINBOARD_PART_NUMBER + string + default "Galileo" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name new file mode 100644 index 0000000..124aa7a --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_INTEL_GALILEO + bool "Galileo" diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc new file mode 100755 index 0000000..3ffba1c --- /dev/null +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100755 index 0000000..ab4f246 --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end diff --git a/src/mainboard/intel/galileo/galileo.html b/src/mainboard/intel/galileo/galileo.html new file mode 100644 index 0000000..6fb75c9 --- /dev/null +++ b/src/mainboard/intel/galileo/galileo.html @@ -0,0 +1,100 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo Gen 2</title> + </head> + <body> + +<h1>Intel® Galileo Gen 2 Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the +util/xcompile/xcompile file to change the machine architecture from i686 to i586 because +the Quark™ processor does not support the instructions introduced with the +Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../../../soc/intel/quark/quark.html">Quark™</a> SoC: +</p> +<ul> + <li><a target="_blank" href="../../../../Documentation/x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../../../soc/intel/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../../../drivers/intel/fsp1_1/1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Gen 2 Board Documentation</h1> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../../../soc/intel/quark/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100755 index 0000000..dfae772 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +}