[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Don't init SMIs or SCIs in psp_verstage

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42765 )

Change subject: soc/amd/common: Don't init SMIs or SCIs in psp_verstage
......................................................................

soc/amd/common: Don't init SMIs or SCIs in psp_verstage

We can't set the SMI or SCI flags in psp verstage, so skip them.

TEST=Build
BUG=b:154142138

Signed-off-by: Martin Roth 
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 12 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/42765/1

diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 419f67a..3169e0e 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -180,6 +180,7 @@
    int gevent_num;
    const struct soc_amd_event *gev_tbl;
    size_t gev_items;
+	const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE);

inter_master = gpio_get_bar() + GPIO_MASTER_SWITCH;
    direction = 0;
@@ -198,7 +199,9 @@
     */
    mem_read_write32(inter_master, 0, GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);

-	soc_get_gpio_event_table(&gev_tbl, &gev_items);
+	if (can_set_smi_flags) {
+		soc_get_gpio_event_table(&gev_tbl, &gev_items);
+	}

for (index = 0; index < size; index++) {
    	gpio = gpio_list_ptr[index].gpio;
@@ -234,11 +237,19 @@
    					AMD_GPIO_CONTROL_MASK);
    			break;
    		case GPIO_SMI_FLAG:
+				/* Can't set SMI flags from PSP */
+				if (!can_set_smi_flags)
+					break;
+
    			mem_read_write32(gpio_ptr, control,
    					INT_SCI_SMI_MASK);
    			program_smi(control_flags, gevent_num);
    			break;
    		case GPIO_SCI_FLAG:
+				/* Can't set SCI flags from PSP */
+				if (!can_set_smi_flags)
+					break;
+
    			mem_read_write32(gpio_ptr, control,
    					INT_SCI_SMI_MASK);
    			get_sci_config_bits(control_flags, &bit_edge,