Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/24973
Change subject: mb/google/fizz: Skip FSP init for UART 0 ......................................................................
mb/google/fizz: Skip FSP init for UART 0
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. Coreboot it setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device.
The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots.
Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/24973/1
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 5eeb03c..e7654cf 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -304,7 +304,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"